The invention relates to semiconductor memories and more particularly to a nonvolatile dynamic memory having lockable cells.
It is well known that an important consideration for nonvolatile memories is that they be able to conserve data even when there is no power supply. Typically, in a flash EEPROM nonvolatile memory, data written into memory cells must be held in the memory cells until an erasure operation is performed to remove the data. However, it is inevitable that the memory will be affected by unpredictable variations such as the fluctuation of its power source voltage or other influences from the external environment. These influences can reduce the stability of the data storage and may even result in the undesirable erasure of data stored in the memory cells. In order to avoid such malfunctions, an additional solution called "erasure lock" has been employed in EEPROMs. Under an erasure lock design, a plurality of lockable cells are arranged correspondent to the word lines of a memory cell array, and control gates of the lockable cells belonging to one page are coupled to each other in common. These lockable cells retain information of either the erasure lock or the erasure unlock.
FIG. 1 shows a schematic of a conventional nonvolatile memory having lockable cells corresponding to one page of a normal memory cell array. The nonvolatile memory comprises an memory cell array 1, a lockable cell array 2, an input output buffer 3, a command control circuit 4, a lock control circuit 5, a controller 6, a voltage control circuit 7, first and second page buffers 8a and 8b, and a detection buffer 9.
The memory cell array 1 (one page) and the lockable cell array are both formed of NAND-typed cell strings and lockable cell array 2 formed of a NAND-typed cell string. A string selection line SSL is coupled to the gates of string selection transistors MS.sub.1 through MS.sub.1 in the memory cell array 1, and is also connected to gate of string selection transistor MLS.sub.1 in the lockable cell array 2. A ground selection line GSL is coupled to the gates of ground selection transistors of the memory cell array 1 and the lockable cell array 2. Word lines WL.sub.1 to WL.sub.8 are coupled to the control gates of memory cells MC.sub.1 through MC.sub.8 and of lockable cells MLC.sub.1 through MLC.sub.8. The word lines WL.sub.1 to WL.sub.8 are connected to the outputs of the voltage control circuit 7, which is operated in response to the output of the controller 6. The controller 6 receives information on the state of the voltage level on lockable bit line LBL through the detection buffer 9.
If an address and a command signal for the erasure lock operation are supplied from outside of the nonvolatile external through input/output buffer 3, the command control circuit 4 activates the lock control circuit 5, and then controller 6 lets voltage control circuit 7 be conducted. By applying a read voltage generated from the voltage control circuit 7 to the word lines, the detected voltage levels on the bit lines of the memory cell array 1 and the lockable cell array 2 are stored in first and second page buffers 8a and 8b and in the detection buffer 9. After these voltage levels are stored, the lock control circuit 4 reads the information held at detection buffer 9 and determines whether a selected lockable cell is an on-cell or an off-cell. If the selected lockable cell (e.g., MLC.sub.1) is an on-cell, it indicates that the page is in the state of erasure unlock, which allows for programming of the page. However, if the selected lockable cell is an off-cell, it indicates that the page in the state of erasure lock.
If the information from the lockable cell array denotes that a page is in a state of erasure unlock, certain operations are performed prior to programming the memory cells of the memory cell array 1 associated with the page, and the lockable cells of the related lockable cell array 2. Data stored in the memory cells and lockable cells of the page to be locked are first transformed to a subsidiary memory region and then all of the cells are completely erased. Thereafter the lockable cells are programmed to become off-cells as of erasure lock state and next the memory cells are programmed with the data temporally stored in the subsidiary memory region. Any page selected to be locked must be put into an erasure mode before programming. Also in the case of converting a locked page to an unlocked page, after data stored in memory cells of a page selected to be unlocked are moved to the subsidiary memory region and then all of the memory cells and lockable cells are erased, the memory cells of the page to be unlocked are programmed with the original data stored in the subsidiary memory region. As described above, the processing manner for the erasure lock in FIG. 1 has a disadvantage in that the erasure operation against the memory cells and lockable cells of the page selected is an essential step prior to programming. This reduces the efficiency for the entire operation as well as for the erasure lock.